The present application relates to the fabrication of semiconductor devices, and more particularly, to the formation of dual work function metal gate structures for a stacked fin complementary metal oxide semiconductor (CMOS) device.
Three-dimensional (3D) monolithic integration in which transistors are stacked on top of each other is a promising approach for continue transistor density scaling. In a 3D stacked fin CMOS device, a self-aligned stack of fins can be formed where the top tier and bottom tier fins are used for devices with opposite conductivity types (i.e., p-type and n-type), respectively. Such an approach not only allows smaller footprint by stacking one type of fin field effect transistors (FinFETs) (e.g., p-type FinFETs) on top of a complementary type of FinFETs (e.g., n-type FinFET), but also permits use of different channel materials for two types of FinFETs simply by bonding appropriate device layers. In a stacked fin CMOS device, the n-type FinFET and the p-type FinFET share a common gate electrode. Because a threshold voltage of a FinFET is primarily determined by the work function of the gate metal used, and in order to obtain a desired threshold voltage for either n-type or p-type FinFET, two meal gate structures having different work functions are typically used. It is challenging, however, to form independently adjustable duel work function metal gate structures in the stacked fin CMOS device due to the difficulty in selective removal of one of the metal gate structures by lithography and etching in vertically stacked devices. Therefore, there remains a need for an improved method for fabricating dual work function metal gate structures for a stacked fin CMOS device that is compatible with existing CMOS process flows.